1. Field of the Invention
This invention relates to an application specific integrated circuit (ASIC) and, more particularly, to an ASIC having a redundancy capability for replacement of defective embedded memory subunits of a memory instance in the ASIC.
2. Prior Art
In the design and production of an ASIC, a compiler, or higher level computer program, is used by an ASIC designer to convert the designer's keystroke inputs from a workstation to tape-out information that is used for generating production masks that are used to fabricate an ASIC chip. An ASIC design can have a number of different functional units provided on a single chip. These functional units include one or more embedded memory instances, or blocks, such as, for example, embedded random access memory (RAM) blocks, that are physically co-located in close proximity to various other types functional blocks on the ASIC.
Sometimes, an embedded memory instance has a defective memory subunit, such as a defective row or a defective input-output (I/O) unit. An I/O unit is a group of several memory columns and a multiplexer that is used to select a particular one of the memory columns for I/O operation. After an ASIC is fabricated and tested, various defective bits (if any) in the memory instances in a particular subunit need to be corrected or replaced by redundant memory circuits. One redundancy technique uses a fuse array that is provided by the compiler to store an address of a defective subunit of an embedded memory instance.
Prior art memory redundancy techniques are focused on stand-alone memories. A stand alone memory chip uses a very limited number of functional units in its design while an ASIC uses a considerably larger number of different functional units in its design. In an ASIC, co-locating a fuse array in the vicinity of a memory instance complicates the design and operation of the ASIC. For example, fuse arrays take up large amounts of chip area and the structure and fabrication of such a fuse array may not be compatible with the structure and fabrication of an ASIC embedded memory instance or other functional blocks located near a embedded memory instance in an ASIC. Consequently, there is a need to provide an improved redundancy architecture for embedded memories in an ASIC chip.